1. Field of the Invention
This invention relates to an improved contact for an integrated circuit structure. More particularly, this invention relates to an improved contact to an electrode such as a bit line adjacent another electrode such as a word line in an integrated circuit structure and a method of making the improved contact.
2. Description of the Related Art
In the conventional construction of integrated circuit structures such as, for example, a dynamic RAM memory cell (DRAM), contact to the bit line had to be separated from the adjacent word line comprising the gate of the memory transistor by a certain distance dictated both by minimum insulation requirements and alignment tolerances. Because of the misalignment possibilities and the deleterious effects of same, alignment tolerance considerations have usually exceeded insulation requirements as far as area used for the contact.
As shown in the prior art structure of FIGS. 1 and 2, conventional construction of contact A between metal bit line B and the source or drain C of the respective memory transistor in D substrate usually required a minimum spacing shown as S between contact A and the adjoining word lines E comprising the gates of the memory transistors. This minimum space S, which was required on all sides of contact A as shown in FIG. 2, was usually about one micron.
In the production of VSLI structures containing thousands of such memory cells, this additional spacing requirement is multiplied many times in terms of the total area needed. Reduction of the space required for each bit line contact without compromising the integrity of the design would therefore be highly desirable.